Description_x000D_ General description_x000D_ Substrate: 150 mm wafer according to semiconductor standard_x000D_ Structure classes: transistors, inverters, and ring oscillators, additional technology test structures, basic circuits_x000D_ Die size: 15 × 15 mm2_x000D_ No. of dies: 56_x000D_ No. of pads: 39 + 2_x000D_ Pad size: 1200 × 800 μm2_x000D_ Gate oxide: 200 nm ± 10 nm_x000D_ Structured layers: 3 (gate, contacts, source/drain)_x000D_ Gate layer: Ti/TiN, Rs about 10Ω/sq_x000D_ Contacts: standard 20 × 20 μm2, R around 20Ω_x000D_ Top layer: 70 nm Au with 10 nm high work function adhesion layer (ITO), by lift-off technique, Rs about 0.65 Ω/sq/ 0.45 Ω/sq_x000D_ Documentation: included in shipment_x000D_ Shadow mask: possible, but not required_x000D_ Probecard: possible, but not required_x000D_ Protection: resist protection layer (AR PC 5000/3.1, soluable in AZ-thinner or acetone)_x000D_ Transistors (11)_x000D_ Connections:_x000D_ • shared gate (2 pads on different chip sides)_x000D_ • shared source (2 pads on different chip sides)_x000D_ • drain for each transistor_x000D_ Measurements_x000D_ • transfer and output characteristics for each transistor to evaluate new organic semiconductors or to monitor organic material fabrication_x000D_ Characterization_x000D_ • designed for parameter extraction to obtain simulation models_x000D_ Description see manual_x000D_ Inverters (4)_x000D_ All 4 inverters are used within the ring oscillator stages or output drivers_x000D_ Connections_x000D_ • shared gate IN for the active transistors (2 pads on different chip sides)_x000D_ • shared gate GEX for the load transistors (2 pads on different chip sides)_x000D_ • shared VSS_x000D_ • VDD and output OUT pads for each inverter_x000D_ Layout_x000D_ • Layout designed for single transistor separation_x000D_ • Channel length of all transistors: L=5 μm_x000D_ Measurements_x000D_ • Inverter (input/output) characteristics for rapid monitoring of organic materials_x000D_ • Supply voltages on VDD and VSS (e.g. for p-type organic material: most positive voltage connected to VDD and ground connected to VSS)_x000D_ • Voltage on IN (gate of active transistor) with value between VDD and VSS_x000D_ • Different voltage on GEX (gate of load transistor) changes driver/load ratios_x000D_ • Important: measure output voltages with high impedance volt meter_x000D_ Ring oscillators (4)_x000D_ • Connections - left edge (2 ring oscillators)_x000D_ • shared gates (GATE_1_2) for all load transistors_x000D_ • shared VSS_x000D_ • VDD and output OUT pads for each oscillator_x000D_ Connections - right edge (2 ring oscillators)_x000D_ • shared gates (GATE_3_4) for all load transistors_x000D_ • shared VSS_x000D_ • VDD and output OUT pads for each oscillator_x000D_ Layout_x000D_ • 7 or 15 ring stages_x000D_ • Simple inverter layout or inverter layout, designed for single transistor separation_x000D_ • Different driver/load ratios_x000D_ • Channel length of all transistors: L=5 μm_x000D_ Measurements_x000D_ • Measure result: oscillation frequency on OUT and calculated inverter delay_x000D_ • No input signal required_x000D_ • Supply voltages on VDD and VSS (e.g. for p-type organic material: most positive voltage connected to VDD and ground connected to VSS)_x000D_ • Different voltage on GEX (gate of load transistors) changes driver/load ratios_x000D_ • Changing these voltage (more positive or more negative than VSS) triggers oscillation_x000D_ • Measure output: high impedance oscilloscope probe required_x000D_ Application_x000D_ For material scientists in the field of organic semiconductors, it is critically important to have standardized device architecture for material analysis._x000D_ One further step in simplifying materials characterization is the analysis of basic logic circuits. Here, up to 36 single transistors are interconnected to inverters and ring oscillators. Monitoring of the active materials then only requires a frequency measure­ment of the ring oscillators which can be automated easily. This prevents the complicated and time-consuming measurement and analysis of the individual transistor characteristic. Further­more, it is not only reliable information about logic capability that is acquired. The dynamic characteristics of the inverters are also determined._x000D_ The layout of a LOFET chip includes an initial block with eleven individual transistors making a complete para-meter extraction for circuit simulation possible. A second block contains four inverters which are replicated in the oscillators. These separately accessible inverter levels enable a detailed analysis of the transient behavior in case the amplification of the individual inverter stages is not sufficient for starting the oscillation of the ring oscillators. The third block contains ring oscillators with either seven or 15 stages. Each ring circuit has a three-stage output amplifier which decouples the oscillation inside the ring from the output terminal and allows a direct frequency measurement without external amplification. The LOFET substrates are also produced in bottom gated architec­ture so that functional circuits require the deposition of the semiconductor layer only._x000D_ Packaging_x000D_ diced wafer on foil with air tight packaging_x000D_ Preparation Note_x000D_ Recommendation for resist removal:_x000D_ To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air)._x000D_ Recommendation for material characterization:_x000D_ If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates._x000D_ Storage and Stability_x000D_ Store the wafers at a cool and dark place and protect them against sun._x000D_ Resist layer was applied to prevent damage from scratches._x000D_ Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire._x000D_ Legal Information_x000D_ Product of Fraunhofer IPMS